Optimizing performance with Performance Accelerator

Server and Cluster Administration Guide for Hitachi NAS Platform

Version
15.1.x
Audience
anonymous
Part Number
MK-92HNAS010-35

The Performance Accelerator feature optimizes throughput and IOPS capacity in the NAS Platform system by enabling very-large-scale integration (VLSI) features in the NAS server. Both throughput and IOPS capacities are significantly increased. To maximize throughput in the VLSI, the PCIe connection between the SI fpga and the Tachyon Fibre Channel controller is increased from four to eight lanes. This lane increase doubles the available bandwidth of the connection, providing greater throughput and speed. Performance Accelerator enhances the IOPS component by increasing the number of cache controllers from one to two, within the SI FPGA, maximizing the available amount of cache controller processing power. If a bottleneck previously existed in the PCIe connection to the Tachyon Fibre Channel controller, or to the SI cache controller, Performance Accelerator might reduce or eliminate such a bottleneck.